This invention pertains to automated manufacturing environments, such as semiconductor manufacturing, and, more particularly, to a method and apparatus for determining metrology sampling decisions based on fabrication simulation.
A semiconductor fabrication facility typically includes numerous processing tools used to fabricate semiconductor devices. The processing tools may include photolithography steppers, etch tools, deposition tools, polishing tools, rapid thermal processing tools, ion implantation tools, and the like. Wafers (or wafer lots) are processed in the tools in a predetermined order and each processing tool modifies the wafers according to a particular operating recipe so that a desired product is formed in or on the wafer. For example, a photolithography stepper may be used to form a patterned layer of photoresist above the wafer. Features in the patterned layer of photoresist correspond to a plurality of features, e.g. gate electrode structures, which will ultimately be formed above the surface of the wafer. When processing of the wafer is complete, the various features formed in or on the wafer, as well as features formed in or on layers that are deposited above the wafer, combined to form the desired product. Exemplary products include processors, memory elements, and the like.
The semiconductor fabrication facility typically also includes metrology tools for collecting data indicative of the physical state of one or more wafers before, during, and/or after processing by the processing tools. Data collected by the metrology tools may be used to characterize the wafer, to detect faults associated with the processing, or to determine the quality of the finished product. For example, a mean critical dimension associated with the various features may be indicative of a performance level of products formed on the wafer and/or the wafer lot. If the wafer state data indicates that the mean critical dimension associated with the feature, e.g., a gate electrode, is on the lower end of an allowable range for such feature sizes, then this may indicate that the product formed on the wafer may exhibit relatively high performance levels. For example, smaller feature sizes in a processor formed on the wafer may be associated with faster processing speeds. Higher performance products may be sold at a higher price, thereby increasing the profitability of the manufacturing operation.
High-volume manufacturing environments may be used to form the different products concurrently. For example, a single semiconductor fabrication facility may be used to form hundreds of different products including processors of varying processing speeds and/or architectures, memory elements of different types (e.g., EEPROM, flash memory, etc.) and/or sizes (e.g., 64 MB, 128 MB, etc), and the like. Wafers associated with each product are typically provided to at least one metrology tool to assess the performance of the products and/or to detect faults associated with processing. Because metrology tools are typically not provided in numbers sufficient to measure all wafers produced, a sampling approach is used.
Conventional metrology sampling plans are predetermined based on the process control information contained in each lot. In other words, lots including the same process control information are considered as a group. Sampling rates are based upon the groups. Product type is one component in the grouping. For example, if grouping A is expected to run 6 wafer lots per week, the metrology sampling plan associated with grouping A may be set to 100% so that all of the wafer lots associated with grouping A are sampled in the appropriate metrology tool. If grouping B is expected to run approximately 200 wafer lots a week, the metrology sampling plan may be set to a much lower value (e.g., 10-20%), so that fewer wafer lots associated with grouping B are provided to the metrology tools and the potential for bottlenecks at the metrology tools is reduced. The metrology tools may also be preconfigured to apply different business rules, filters, and/or weighting factors when performing metrology on grouping A or grouping B.
Changes in the anticipated processing volume associated with different products can cause serious problems for a semiconductor fabrication facility. For example, if demand for grouping A suddenly and/or unexpectedly increases and the semiconductor fabrication facility begins to run approximately 200 wafer lots per week to produce grouping A, the predetermined sampling plan will continue to indicate that 100% of the wafer lots associated with grouping A are to be sampled by the metrology tools. Consequently, a severe bottleneck may form at the metrology tools, which may reduce the production efficiency for grouping A, potentially resulting in lost profits for a product that is in high demand. Conversely, if the volume of wafer lots associated with grouping B drops, the lower sampling rate may not be sufficient to maintain the quality of grouping B and/or to detect faults that may occur during processing of grouping B.
In a conventional semiconductor fabrication facility, engineers typically change the predetermined sampling plans manually when the production volume associated with a product is expected to change. However, changing the sampling plans manually is typically time-consuming, labor-intensive, and may even require that production be halted while the new sampling plans are determined and implemented in the semiconductor fabrication facility. Moreover, engineers may not be able to anticipate all changes in the production volumes associated with different products and therefore may not be able to change the predetermined sampling plans to account for these unanticipated changes.
This section of this document is intended to introduce various aspects of art that may be related to various aspects of the present invention described and/or claimed below. This section provides background information to facilitate a better understanding of the various aspects of the present invention. It should be understood that the statements in this section of this document are to be read in this light, and not as admissions of prior art. The present invention is directed to overcoming, or at least reducing the effects of, one or more of the problems set forth above.